Shimabukuro Katsuhiko

写真a

Title

Associate Professor

Researcher Number(JSPS Kakenhi)

90253947
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Current Affiliation Organization 【 display / non-display 】

  • Duty   University of the Ryukyus   Faculty of Engineering   School of Engineering_Electronic and Communication Engineering Program   Associate Professor  

  • Concurrently   University of the Ryukyus   Graduate School of Engineering and Science   Associate Professor  

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Academic degree 【 display / non-display 】

  • Tohoku University -  Doctor of Engineering

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External Career 【 display / non-display 】

  • 1997.03
    　
    　

    University of the Ryukyus, Faculty of Engineering, Department of Electrical and Electronics Engineering, Electronics and Elctronic Materials, Associate Professor  

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Research Interests 【 display / non-display 】

  • Multiple-Valued Digital Processing System,Parallel Processing VLSI,Arithmetic Circuit Design

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Research Theme 【 display / non-display 】

  • Study on Multiple-Valued VLSI Processors Based on Parallel Architecture

  • Study on Highly Parallel Arithmetic Circuit Design Based on Residue Number Systems

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Published Papers 【 display / non-display 】

  • Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic

    Shimabukuro, K; Kameyama, M

    2017 IEEE 47TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2017)     19 - 24   2017 [ Peer Review Accepted ]

    Type of publication: Research paper (scientific journal)

    • Access this article
      DOI

  • Multiple-Valued Mask-Programmable Logic Array Using One Transisor Universal-Literal Circuits

    Katsuhiko Shimabukuro et al.

    Proc of the 31st ISMVL ( その他の出版社 )    2001.03

    Type of publication: Research paper (other science council materials etc.)

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