NAGATA Yasunori

写真a

Title

Professor

Researcher Number(JSPS Kakenhi)

50208021

Date of Birth

1960

Laboratory Address

1 Senbaru,Nishihara,Okinawa

Mail Address

E-mail address

Laboratory Phone number

+81-98-895-8687

Laboratory Fax number

+81-98-895-8687
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Current Affiliation Organization 【 display / non-display 】

  • Duty   University of the Ryukyus   Faculty of Engineering   School of Engineering_Electronic and Communication Engineering Program   Professor  

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Study abroad experiences 【 display / non-display 】

  • 1999.05
    -
    2000.03

    University of Victoria  

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Academic degree 【 display / non-display 】

  • Meiji University -  Doctor of Engineering

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External Career 【 display / non-display 】

  • 2008.04
    　
    　

    University of the Ryukyus, Faculty of Engineering, Professor  

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Research Interests 【 display / non-display 】

  • 計算機科学,情報科学

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Published Papers 【 display / non-display 】

  • A Music Score Automatic Page Turning System exploiting Eyes-Tracking.

    Taiki Nakayama, Yasunori Nagata

    IEEJ     2023.09

    Type of publication: Research paper (research society, symposium materials, etc.)

  • Visual Inspection System for Piston-Ring Parts via Machine Learning

    Taira Takuma, Zheng Wanxian, Miyagi Takeshi, Nagata Yasunori

    IEEJ Transactions on Industry Applications ( The Institute of Electrical Engineers of Japan )  143 ( 2 ) 101 - 105   2023.02 [ Peer Review Accepted ]

    Type of publication: Research paper (scientific journal)

    　View Summary

    <p>Development of a system that can automatically detect appearance defects of piston-ring components of the engine cylinder caused during the coating process. In the proposed system, piston-rings are sent from the feeder to conveyor belt, and an image captured by camera. Subsequently, the image is cut along with the shape of ring into small images. A convolution neural network (CNN) model to classify which piston-ring is a normal and anomaly. Finally, a robot arm is utilized to remove the anomaly piston-ring from the conveyor belt.</p><p>In our previous experiment, when a GPU-based computer was used to process images, the system could achieve approximately 90-100% accuracy based on the type of defects. To reduce the costs of system, we study single-board computer (SBC) with Google Edge TPU USB Accelerator to classify images, which exhibits good potential to replace GPU-based processing. Furthermore, this paper also proposes some approaches to improve processing speed when using proposes low-cost SBC platform.</p>

  • An Explanatory Study Approach, Using Machine Learning to Forecast Solar Energy Outcome

    Agada Ihuoma Nkechi, Yasunori Nagata

    Journal of Energy and Power Engineering ( DAVID PUBLISHING )  16   81 - 89   2022.04 [ Peer Review Accepted ]

    Type of publication: Research paper (scientific journal)

  • Hysterisial Variable-Threshold MOS Gates

    Nagata Yasunori, Kawaguchi Mayuka F., Yamada Chikatosi, Miyagi Takeshi

    IEEJ Transactions on Electronics, Information and Systems ( The Institute of Electrical Engineers of Japan )  139 ( 9 ) 958 - 963   2019.09 [ Peer Review Accepted ]

    Type of publication: Research paper (scientific journal)

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    <p>Asynchronous circuits are a technique in order to solve the some serious synchronous circuits' problems such as clock skew, power consumption and electromagnetic noise. In this paper, we designed histerisial variable-threshold gates based on neuron MOS transistors for asynchronous circuits. The proposed hysteresial variable-threshold gates are also expected usuful for neural networks or machine larning for the hysteresis, that is memory, characteristics. The developed gates having variable-threshold operations can be used to set a threshold of a neuron. The simulation results of hysteresial variable-threshold gates are provided with SPICE simulator. The synthesized hysterisial variable-threshold gates has three gate-inputs and two control wires. Then asynchronous half-adder is demonstrated as an arithmetic circuit example.</p>

  • Design and Synthesis of Ternary CMOS Logic Circuits and D-Element

    Nagata Yasunori, Kawaguchi Mayuka F., Yamada Chikatoshi

    IEEJ Transactions on Industry Applications ( The Institute of Electrical Engineers of Japan )  139 ( 2 ) 143 - 148   2019.02 [ Peer Review Accepted ]

    Type of publication: Research paper (scientific journal)

    　View Summary

    <p>In this paper, a design technique for ternary logic function circuits based on CMOS design are proposed. The circuits operate as B-ternary (binaric ternary) logic functions that are useful in asynchronous systems or self-checking circuits of fault-tolerant systems. Further, a special logic circuit, D-element, is proposed. D-element is designed for asynchronous systems like Mullers C-element in binary circuits. The circuits' SPICE simulations are provided to show their efficacy.</p>

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